GSM transceiver with time division duplexed operations for receiving data, monitoring signal strength and transmitting data during a single time frame

ABSTRACT

A Global System for Mobile (GSM) cellular system transceiver with time division duplexed operations for receiving a data signal, monitoring received signal strength and transmitting a data signal during a single time frame. Multiple data registers are used to store the phase lock loop (PLL) frequency control data, e.g., during the last time slot (slot  7 ) of the prior time frame (or elsewhere in the prior time frame where time permits). Also during slot  7  of the prior time frame, the PLL is programmed using the first data set for the data reception operation to be performed during one or more of the initial time slots (e.g., time slots  0-3 ) of the present time frame. During the next time slot (e.g., slot  4 ), the PLL is programmed using the second data set for the signal strength monitoring operation to be performed during that same time slot. During the next time slot (e.g., slot  5 ), the PLL is programmed using the third data set for the data transmission operation to be performed beginning in that same time slot. By prestoring all three PLL frequency control data sets, such data sets are immediately available when later programming the PLL, thereby reducing the PLL setup time needed prior to each use. Consequently, an integer PLL can be used instead of a fractional PLL while still achieving a sufficiently fast combined setup and lock time, thereby minimizing integrated circuit area and power requirements.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to time division multiple access (TDMA)communication systems, such as Global System for Mobile (GSM)transceivers, and in particular, to GSM transceivers capable ofreceiving General Package Radio Service (GPRS) data.

2. Description of the Related Art

As is well known, GSM is a second-generation cellular communicationsystem standard that was developed to solve problems associated with theoriginal analog cellular communication systems in Europe. GSM usesdigital communication techniques, including frequency division duplexing(FDD) and a combination of time division multiple access (TDMA) andfrequency division multiple access (FDMA) techniques to allowsimultaneous access by base stations to multiple users.

Referring to FIG. 1, each communication channel in a GSM system isaccessed on a time shared basis and is divided into time frames, whichare 4.615 milliseconds long. Each time frame is divided into eight timeslots 0-7, each of which is approximately 577 microseconds long. Duringnormal used, i.e., during voice transmission and reception, thedigitized voice information is packetized and transmitted duringdifferent time slots. For example, a receive operation for acceptingincoming voice data may take place during time slot 0, while a transmitoperation for sending voice data may take place during time slot 3.Additionally, a monitor function may be performed, e.g., during timeslot 6, during which the signal strength for signals arriving fromdifferent base stations is monitored for power level. It is necessary toseparate these active time slots 0, 3, 6 by two or more unused timeslots so as to allow the common, or shared, phase lock loop (PLL) withinthe GSM handset to be set up and locked at the correct frequency for thereceive, transmit or monitoring function. Minimum set up and lock timesare required due to the use of integer PLL circuits. These integer PLLcircuits are generally preferred over fractional PLL circuits since theyare less complex and hence require significantly less integrated circuitarea and less DC power.

Referring to FIG. 2, the transmit and receive functions of a GSM handsetcan be implemented using conventional transmitter and receiver circuitarchitectures. In this example, such functions can be implemented in anintegrated form using a circuit 100 such as the LMX3411 manufactured byNational Semiconductor Corporation of Santa Clara, Calif. As discussedin more detail below, this transmitter uses a modulation synthesizerarchitecture to convert an I/Q baseband representation to the desiredtransmit frequency. The receiver is a dual conversion receiver withchannel selectivity provided by a SAW filter at the intermediatefrequency (IF). In this particular integrated circuit 100, most of thetransmitter and receiver functions are integrated within the chip.

Incoming signals received by the antenna 102 are forwarded to the lownoise amplifier (LNA) stage 104, the bias for which is controlled by acontrol circuit within the chip 100. A band pass filter stage 106filters the amplified signal prior to its frequency down conversion inthe RF mixer stage 108 which is driven by a local oscillator signalprovided by the RF PLL circuit 110 which uses an integer PLL 112. Theresulting IF signal is filtered by an external SAW band pass filter 112which provides the channel selectivity. The filtered IF signal is thenamplified by an IF amplifier 114 having a programmable signal gain.

The amplified IF signal is converted to a quadrature representation inan I/Q mixer stage 116. The local oscillator signal is provided by theIF PLL circuit 114 which also uses an integer PLL 116. The resulting Iand Q signals are low pass filtered and further amplified in a digitallyprogrammable gain amplifier stage 118.

The transmitter architecture is based on a closed loop modulation ofwide band frequency synthesizer. A wide band PLL 122 modulates anexternal voltage control oscillator (VCO) 126 having a loop filterbandwidth, as determined by the loop filter 124, sufficiently wide tocorrectly track the modulation inserted into the loop. A low pass filter128 is used to filter out harmonics of the output signal prior to itsamplification by the power amplifier 130 and transmission via theantenna 102. The output signal is also fed back to the transmitter downconversion mixer 118, which also receives its local oscillator signalfrom the RF PLL circuit 110. The resulting IF signal is band passfiltered and converted to a quadrature representation in the transmitquadrature mixer stage 120 in accordance with the outgoing signal dataintended for transmission. These I and Q signals are low pass filteredand provided to the wide band PLL 122, along with the shared signal fromthe IF PLL circuit 114.

As discussed in more detail below, the aforementioned control andprogramming functionality is achieved by a way of an interface andcontrol stage 120 which provides the programmable control data for thevarious control stages and programmable circuits.

Referring to FIG. 3, the interface and control stage 120 includes a set200 of seven registers 201-207, which are used to store strings ofcontrol data ranging from 8 to 24 bits in length. The first register 201controls power to the various stages of the circuit 100. The secondregister 202 provides the gain control information for the variousprogrammable gain stages. The third 203 and fourth 204 registers storethe control data for the N-counters within the RF 112 and IF 116 PLLstages (FIG. 2). The fifth register 205 stores the control data for theR-counters within the PLL stages 112, 116. The sixth register 206 storesthe control data for the wide band PLL stage 122. The last register 207stores miscellaneous control data used for various other functionswithin the circuit 100.

While the above-discussed transceiver architecture and control workswell for most GSM services, particularly voice transmission andreception, the introduction of data services, such as GPRS, presents aproblem concerning the lock time requirement of the PLL circuits. Forexample, for Class 12 GPRS, the worst case PLL lock time requirement isapproximately 200 microseconds when using the above-discussedconventional approach for programming the receiver. In order to achievethis 200 microsecond lock time, the PLL circuits would need to befractional PLL circuits which require significantly more integratedcircuit area and DC power than integer PLL circuits such as thosepresently used in most cases. This means, that for normal voiceoperation where this faster lock time is not required, the powerconsumption of the handset is nonetheless increased significantly.

More specifically, a Class 12 GPRS operation will use up to five of theavailable eight time slots in a GSM time frame for data communication.For example, four receive slots and one transmit slot may be used,resulting in the following analysis (it will be understood that otherpermutations of receive and transmit slots may also be used and willyield the same analysis). As is known, a GSM time frame has eight timeslots, each of which is approximately 577 microseconds. In this example,four receive operations, one transmit operation and one power monitoroperation must be completed within the one time frame. Additionally, thetransceiver needs to be set up for the subsequent time frame.Technically, there are two time slots allowed between the end of thereceive operation and the beginning of the transmit operation within thetime frame. However, since a GSM system is synchronized to the basestation, the transmit signal may need to be transmitted prior to theactual start of the time slots within the intended handset so as toensure that the signal arrives at the base station as the correct time.This is called “timing advance.” The maximum specified timing advance isapproximately 232 microseconds, or 63 bits, so the time interval betweenwhen the receive operation is completed and the transmit operation isbegun may be reduced by up to 232 microseconds.

Additionally, when the handset needs to monitor different base stationsfor power level (often referred to as a received signal strengthindicator, or RSSI, function), this is normally done between the receiveand transmit operations (provided that there are at least two time slotsbetween the receive and transmit time slots). The typical time durationof the monitor operation is approximately 232 microseconds, or the timeequivalent of 64 bits. Accordingly, in order to achieve this, thetransceiver must be programmed twice and the RF synthesizers must belocked twice within the remaining time.

The timing analysis is as follows. Two time slots total approximately1,154 microseconds. Subtracted from this total time are the maximumtiming advance of 232 microseconds and the duration of the monitoroperation of 236microseconds. Further subtracted from this total timeare two 8-bit write operations (for programming the power controlregisters in order to turn the receive and transmit sections on and off)totaling 16 microseconds (assuming a net programming speed of 1 bit permicrosecond to include microprocessor calculation and setup). Thisleaves a net available time of 666 microseconds for setting up andlocking the RF PLL stage two times, or 333 microseconds per PLLprogramming operation. With a net programming speed of 1 bit permicrosecond and approximately 100 bits required to be written for eachoperation, this leaves a maximum time of 233 microseconds available forachieving phase lock. For the conventional integer PLL circuits used,this is not enough time for achieving phase lock.

Indeed, this time may be even less where a separate monitor, or RSSI,section must be cycled. In other words, there may be four 8-bit writeoperations required: (1) power down the receive section; (2) power upthe monitor section; (3) power down the monitor section; and (4) powerup the transmit section.

Accordingly, it would be desirable to have an improved technique foraccommodating Class 12 GPRS operations within a GSM handset withoutrequiring the increased cost and power requirements associated with theneed for using fractional PLL circuits to met the faster phase lock timerequirements.

SUMMARY OF THE INVENTION

A GSM receiver with time division duplexed operations for receiving adata signal, monitoring received signal strength and transmitting a datasignal during a single time frame in accordance with one embodiment ofthe present invention uses a PLL control stage having multiple registersfor storing control data that is preprogrammed prior to initiation ofthe receive, monitoring and transmit operations. These registers arepreprogrammed with the control data during a time slot (e.g., time slot7) within the prior time frame. This allows the programming for settingup the RF PLL to be reduced to the 16 bits (8 bits for power down plus 8bits for power up) for the power control registers, thereby leaving morethan 300 microseconds available for achieving phase lock and, in turn,thereby allowing standard integer PLL circuits to be used within thetransceiver.

An apparatus including a GSM transceiver with time division duplexedoperations for receiving a data signal and transmitting a data signalduring a single time frame in accordance with one embodiment of thepresent invention includes a receiver stage, a transmitter stage, asignal generator stage and a controller stage. The receiver stage isconfigured to receive a local signal and in accordance therewith receiveand frequency convert an incoming data signal during a first portion ofa plurality of time slots within a present time frame and in accordancetherewith provide a frequency converted incoming data signal. Thetransmitter stage is configured to receive the local signal and inaccordance therewith receive and frequency convert an outgoing datasignal during a second portion of the plurality of time slots within thepresent time frame and in accordance therewith provide a frequencyconverted outgoing data signal. The signal generator stage, coupled tothe receiver and transmitter stages, is configured to receive first andsecond sets of control data and in accordance therewith provide thelocal signal at first and second signal frequencies during the first andsecond portions, respectively, of the plurality of time slots within thepresent time frame. The controller stage, coupled to the signalgenerator stage, is configured to receive and store the first and secondsets of control data during a prior time frame and to provide to thesignal generator stage one of the first and second sets of control dataduring a time interval between the first and second portions of theplurality of time slots within the present time frame.

A method for time division duplexing operations within a GSM transceiverfor receiving a data signal and transmitting a data signal during asingle time frame in accordance with another embodiment of the presentinvention includes the steps of:

storing first and second sets of frequency control data during a priortime frame;

reading the first set of frequency control data during a first timeinterval and in accordance therewith generating a local signal at afirst frequency;

receiving and frequency converting an incoming data signal in accordancewith the local signal at the first frequency during a first portion of aplurality of time slots within a present time frame and in accordancetherewith generating a frequency converted incoming data signal;

reading the second set of frequency control data during a second timeinterval and in accordance therewith generating the local signal at asecond frequency; and

receiving and frequency converting an outgoing data signal in accordancewith the local signal at the second frequency during a second portion ofthe plurality of time slots within the present time frame and inaccordance therewith generating a frequency converted outgoing datasignal;

wherein one of the first and second time intervals is between the firstand second portions of the plurality of time slots within the presenttime frame.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a timing diagram depicting the time slots within a GSM timeframe.

FIG. 2 is a functional block diagram of a conventional GSM transceiverarchitecture.

FIG. 3 is a diagram depicting the control data registers used in theinterface and control block of the circuit of FIG. 2.

FIG. 4 is a diagram depicting the multiple control data registers usedin a GSM transceiver in accordance with one embodiment of the presentinvention.

FIG. 5 is a timing diagram for the time division duplexed operations forreceiving a data signal, monitoring received signal strength andtransmitting a data signal within a single GSM time frame in accordancewith one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 4, the set 300 of registers for a GSM transceiver inaccordance with the present invention includes three registers 301 a,301 b, 301 c for power control, three registers 302 a, 302 b, 302 c forgain control, three registers 303 a, 303 b, 303 c for the N-counter datafor the RF PLL, and two registers 304 a, 304 b for the N-counter datafor the IF PLL. By programming power control register 301 a, the valuesstored in gain control register 302 a, RF PLL N-counter register 303 aand IF PLL N-counter register 304 a are activated. Similarly for powercontrol register 301 b and power control register 301 c. (The IF PLLonly requires two registers 304 a, 304 b since it uses one fixedfrequency for transmission and another fixed frequency for reception.)Therefore, only a single write operation involving eight bits to thepower control register will be required to select an operation likeenabling the RF PLL. Accordingly, a simple timing analysis demonstratesthat phase lock by the RF PLL can begin immediately after completion ofthe receive operation.

Further in accordance with the presently claimed invention, threeadditional registers (not shown) may be included where an additionalmonitor, or RSSI, operation is desired (e.g.,receive—monitor—transmit—monitor): one more register 301 d for powercontrol; one more register 302 d for gain control; and one more register303 d for N-counter data for the RF PLL.

Still further in accordance with the presently claimed invention, onecommon power control register 301 can be used, rather than three or moreseparate registers 301 a, 301 b, 301 c, 301 d, with indexing used toidentify the appropriate gain control register 302 and counter registers303, 304 to be used during any specific time interval. For example,within an indexing section of the common power control register 301 thebit pattern “00” could be used to designate the use of gain controlregister 302 a and N-counter register 303 a, the bit pattern “01” couldbe used to designate the use of gain control register 302 b andN-counter register 303 b, and so on.

Referring to FIG. 5, the timing for the above-discussed reading andwriting of the data registers 300 (FIG. 4), as well as the enablementand disablement of the RF and IF synthesizers and receive and transmitoperations are as shown. Initial programming of the transceiver controldata registers 300 is done during the prior time frame, e.g., during thelast time slot. During this time interval, the three gain controlregisters 302 a, 302 b, 302 c and the three PLL registers 303 a, 303 b,303 c need to be programmed. (The IF PLL registers are only written oncedue to the use of fixed frequencies in the transmit and receiveoperations.)

The timing analysis for programming during the prior time frame is asfollows. The total time available in the time slot is 577 microseconds.From this is subtracted 8 microseconds for an 8-bit programmingoperation to turn off all transceiver stages. Further subtracted is 120microseconds for programming five registers of 24 bits each (2 gainregisters and 3 PLL N-counter registers). Still further subtracted is 8microseconds for an 8-bit programming operation for initiating the phaselock operation for the present time frame. This leaves 441 microsecondsof time remaining for setting up and locking the RF PLL. With 300microseconds required for achieving phase lock, the setup time availableis 141 microseconds, which is more than sufficient for setting up theprogramming of the registers (since the actual programming time hasalready been subtracted out as part of the aforementioned 120microsecond register setup time).

The foregoing discussion has used, as an example, an operations sequencewhereby data is received, received signal strength is monitored and datais transmitted, in that order. However, it will be understood thatsignal strength monitoring need not necessarily be done, in which casefewer control data registers are needed, and the data reception,transmission and signal strength monitoring can be performed in anyorder or as many times as desired. What is important is that anappropriate number of control data registers are used to provide forpreprogramming of the necessary control data during a time slot in theprior frame, thereby providing immediate access for all control dataduring the present time frame on an as-needed basis.

Various other modifications and alterations in the structure and methodof operation of this invention will be apparent to those skilled in theart without departing from the scope and spirit of the invention.Although the invention has been described in connection with specific,preferred embodiments, it should be understood that the invention asclaimed should not be unduly limited to such specific embodiments. It isintended that the following claims define the scope of the presentinvention and that structures and methods within the scope of theseclaims and their equivalents be covered thereby.

What is claimed is:
 1. An apparatus including a GSM transceiver withtime division duplexed operations for receiving a data signal andtransmitting a data signal during a single time frame, comprising: areceiver stage configured to receive a local signal and in accordancetherewith receive and frequency convert an incoming data signal during afirst portion of a plurality of time slots within a present time frameand in accordance therewith provide a frequency converted incoming datasignal; a transmitter stage configured to receive said local signal andin accordance therewith receive and frequency convert an outgoing datasignal during a second portion of said plurality of time slots withinsaid present time frame and in accordance therewith provide a frequencyconverted outgoing data signal; a signal generator stage, coupled tosaid receiver and transmitter stages, configured to receive first andsecond sets of control data and in accordance therewith provide saidlocal signal at first and second signal frequencies during said firstand second portions, respectively, of said plurality of time slotswithin said present time frame; and a controller stage, coupled to saidsignal generator stage, configured to receive and store said first andsecond sets of control data during a prior time frame and to provide tosaid signal generator stage one of said first and second sets of controldata during a first time interval between said first and second portionsof said plurality of time slots within said present time frame.
 2. Theapparatus of claim 1, wherein said receiver stage comprises: a frequencyconversion stage configured to frequency convert said incoming datasignal and in accordance therewith provide said frequency convertedincoming data signal; and a quadrature mixer stage, coupled to saidfrequency conversion stage, configured to receive and convert saidfrequency converted incoming data signal to a quadrature baseband datasignal.
 3. The apparatus of claim 1, wherein said transmitter stagecomprises: a quadrature mixer stage configured to receive and convertsaid outgoing data signal to a quadrature data signal; and a frequencyconversion stage, coupled to said quadrature mixer stage, configured toreceive said local signal and in accordance therewith receive andfrequency convert said quadrature data signal and in accordancetherewith provide said frequency converted outgoing data signal.
 4. Theapparatus of claim 1, wherein said signal generator stage comprises aninteger phase lock loop circuit.
 5. The apparatus of claim 4, whereinsaid controller stage comprises: a first data register configured tostore said first set of control data; and a second data registerconfigured to store said second set of control data.
 6. The apparatus ofclaim 4, wherein said first time interval has a duration which is lessthan one of said plurality of time slots within said present time frame.7. The apparatus of claim 1, wherein said controller stage comprises: afirst data register configured to store said first set of control data;and a second data register configured to store said second set ofcontrol data.
 8. The apparatus of claim 1, wherein said first timeinterval has a duration which is less than one of said plurality of timeslots within said present time frame.
 9. The apparatus of claim 1,wherein: said receiver stage is further configured to monitor anotherincoming signal during a third portion of said plurality of time slotswithin said present time frame and in accordance therewith provide anindication of a signal strength of said another incoming signal; saidsignal generator stage is further configured to receive a third set ofcontrol data and in accordance therewith provide said local signal at athird signal frequency during said third portion of said plurality oftime slots within said present time frame; and said controller stage isfurther configured to receive and store said third set of control dataduring said prior time frame and to provide to said signal generatorstage another of said first, second and third sets of control dataduring a second time interval between said first and third portions ofsaid plurality of time slots within said present time frame.
 10. Theapparatus of claim 9, wherein said controller stage comprises: a firstdata register configured to store said first set of control data; asecond data register configured to store said second set of controldata; and a third data register configured to store said third set ofcontrol data.
 11. The apparatus of claim 9, wherein each of said firstand second time intervals has a duration which is less than one of saidplurality of time slots within said present time frame.
 12. An apparatusincluding a GSM transceiver with time division duplexed operations forreceiving a data signal and transmitting a data signal during a singletime frame, comprising: receiver means for receiving a local signal andin accordance therewith receiving and frequency converting an incomingdata signal during a first portion of a plurality of time slots within apresent time frame and in accordance therewith providing a frequencyconverted incoming data signal; transmitter means for receiving saidlocal signal and in accordance therewith receiving and frequencyconverting an outgoing data signal during a second portion of saidplurality of time slots within said present time frame and in accordancetherewith providing a frequency converted outgoing data signal; signalgenerator means for receiving first and second sets of control data andin accordance therewith providing said local signal at first and secondsignal frequencies during said first and second portions, respectively,of said plurality of time slots within said present time frame; andcontroller means for receiving and storing said first and second sets ofcontrol data during a prior time frame and for providing to said signalgenerator stage one of said first and second sets of control data duringa first time interval between said first and second portions of saidplurality of time slots within said present time frame.
 13. Theapparatus of claim 12, wherein said receiver means comprises: frequencyconversion means for frequency converting said incoming data signal andin accordance therewith providing said frequency converted incoming datasignal; and quadrature mixer means for receiving and converting saidfrequency converted incoming data signal to a quadrature baseband datasignal.
 14. The apparatus of claim 12, wherein said transmitter meanscomprises: quadrature mixer means for receiving and converting saidoutgoing data signal to a quadrature data signal; and frequencyconversion means for receiving said local signal and in accordancetherewith receiving and frequency converting said quadrature data signaland in accordance therewith providing said frequency converted outgoingdata signal.
 15. The apparatus of claim 12, wherein said signalgenerator means comprises integer phase lock loop means.
 16. Theapparatus of claim 15, wherein said controller means comprises: firstdata storage means for storing said first set of control data; andsecond data storage means for storing said second set of control data.17. The apparatus of claim 15, wherein said first time interval has aduration which is less than one of said plurality of time slots withinsaid present time frame.
 18. The apparatus of claim 12, wherein saidcontroller means comprises: first data storage means for storing saidfirst set of control data; and second data storage means for storingsaid second set of control data.
 19. The apparatus of claim 12, whereinsaid first time interval has a duration which is less than one of saidplurality of time slots within said present time frame.
 20. Theapparatus of claim 12, wherein: said receiver means is further forreceiving said local signal and in accordance therewith monitoringanother incoming signal during a third portion of said plurality of timeslots within said present time frame and in accordance therewithproviding an indication of a signal strength of said another incomingsignal; said signal generator means is further for receiving a third setof control data and in accordance therewith providing said local signalat a third signal frequency during said third portion of said pluralityof time slots within said present time frame; and said controller meansis further for receiving and storing said third set of control dataduring said prior time frame and for providing to said signal generatorstage another of said first, second and third sets of control dataduring a second time interval between said first and third portions ofsaid plurality of time slots within said present time frame.
 21. Theapparatus of claim 20, wherein said controller means comprises: firstdata storage means for storing said first set of control data; seconddata storage means for storing said second set of control data; andthird data storage means for storing said third set of control data. 22.The apparatus of claim 20, wherein each of said first and second timeintervals has a duration which is less than one of said plurality oftime slots within said present time frame.
 23. A method for timedivision duplexing operations within a GSM transceiver for receiving adata signal and transmitting a data signal during a single time frame,comprising the steps of: storing first and second sets of frequencycontrol data during a prior time frame; reading said first set offrequency control data during a first time interval and in accordancetherewith generating a local signal at a first frequency; receiving andfrequency converting an incoming data signal in accordance with saidlocal signal at said first frequency during a first portion of aplurality of time slots within a present time frame and in accordancetherewith generating a frequency converted incoming data signal; readingsaid second set of frequency control data during a second time intervaland in accordance therewith generating said local signal at a secondfrequency; and receiving and frequency converting an outgoing datasignal in accordance with said local signal at said second frequencyduring a second portion of said plurality of time slots within saidpresent time frame and in accordance therewith generating a frequencyconverted outgoing data signal; wherein one of said first and secondtime intervals is between said first and second portions of saidplurality of time slots within said present time frame.
 24. The methodof claim 23, wherein said step of receiving and frequency converting anincoming data signal in accordance with said local signal at said firstfrequency during a first portion of a plurality of time slots within apresent time frame and in accordance therewith generating a frequencyconverted incoming data signal comprises: frequency converting saidincoming data signal and in accordance therewith providing saidfrequency converted incoming data signal; and converting said frequencyconverted incoming data signal to a quadrature baseband data signal. 25.The method of claim 23, wherein said step of receiving and frequencyconverting an outgoing data signal in accordance with said local signalat said second frequency during a second portion of said plurality oftime slots within said present time frame and in accordance therewithgenerating a frequency converted outgoing data signal comprises:converting said outgoing data signal to a quadrature data signal; andreceiving said local signal and in accordance therewith receiving andfrequency converting said quadrature data signal and in accordancetherewith providing said frequency converted outgoing data signal. 26.The method of claim 23, wherein said steps of reading said first, secondand third sets of frequency control data during said first, second andthird time intervals and in accordance therewith generating said localsignal at said first, second and third frequencies, respectivelycomprise generating said local signal at said first, second and thirdfrequencies with an integer phase lock loop.
 27. The method of claim 26,wherein said step of storing first and second sets of frequency controldata during a prior time frame comprises storing said first and secondsets of frequency control data in first and second data registers. 28.The method of claim 26, wherein said one of said first and second timeintervals has a duration which is less than one of said plurality oftime slots within said present time frame.
 29. The method of claim 23,wherein said step of storing first and second sets of frequency controldata during a prior time frame comprises storing said first and secondsets of frequency control data in first and second data registers. 30.The method of claim 23, wherein said one of said first and second timeintervals has a duration which is less than one of said plurality oftime slots within said present time frame.
 31. The method of claim 23,further comprising the steps of: storing a third set of frequencycontrol data during said prior time frame; reading said third set offrequency control data during a third time interval and in accordancetherewith generating said local signal at a third frequency; andmonitoring another incoming signal in accordance with said local signalat said third frequency during a third portion of said plurality of timeslots within said present time frame; wherein another of said first,second and third time intervals is between said first and third portionsof said plurality of time slots within said present time frame.
 32. Themethod of claim 31, wherein said steps of storing first, second andthird sets of frequency control data during a prior time frame comprisesstoring said first, second and third sets of frequency control data infirst, second and third data registers.
 33. The method of claim 31,wherein said one and said another of said first, second and third timeintervals each has a duration which is less than one of said pluralityof time slots within said present time frame.